◆Knowledge in the area of Digital Electronics and writing synthesizable RTL models in Verilog HDL.
◆Experience in writing reusable testbenches in System Verilog and UVM (Including functional coverage and assertion-based verification).
◆Good knowledge of DFT concepts
◆Knowledge of SPI protocol.
◆Familiar with industry-standard tools like Xilinx ISE(1 4.7), Riviera Pro, QuestaSim and Tessent
◆ Perl for scripting.